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Achieving required performance goals within the constraints of real designs (limited board real estate, parts placement
for thermo control, PWB manufacturability, etc..) are key to a successful system. In order to address these types of
high-speed design issues PCB Layout ONLY! works very closely with one of the world's foremost signal integrity
engineers, Robert Cutler. Robert develops CAD layout rules based on simulation results and works closely with our PCB
Designers in order to ensure that formulated design guidelines are properly implemented and that performance vs.
routeability tradeoffs can be made in real time with minimal schedule impact.
As part of his work, Robert was instrumental in the development of the CompactPCI specification that was accepted by
the PICMG as of 12/1/95. A unique termination scheme was developed that effectively damps the bus without adversely
impacting bus speed. GigE, KR, PCIeG2, XAUI, and serial channels up to 12+Gbps are among the technologies that he is
simulating and helping to implement in telecom and networking systems. This work involves modeling passive channels in
the frequency domain using various board substrates (FR406, Nelco 4000-13/13SI, Megtron 6, etc.) and connector systems
to help tradeoff performance vs. cost for the specific design. 3D modeling of via and launch structures is performed
using Ansoft HFSS, a 3D field solver. Robert’s work includes simulating DDR2 & DDR3 interfaces using both modules and
stand alone SDRAM chips.
Robert has been consulting in the field of interconnection technology since 1984 and his experience includes electrical
design, packaging, and production. The primary focus of his work is simulation and analysis of high-speed interconnect
at both the board and backplane level. Robert holds a B.S. in Electrical Engineering from Carnegie-Mellon University.
Published articles include:
Reducing Development Time in High Performance Computing Systems for the High Performance Computing Symposium in
1995.
Simulating Hot Swap in CompactPCI in January 1999 issue of Computer Design.
Reducing Chassis System Costs Without Sacrificing Performance and Bandwidth in the October 2003 EE Times Net Seminar
series.
A partial list of signal integrity analysis clients includes:
for thermo control, PWB manufacturability, etc..) are key to a successful system. In order to address these types of
high-speed design issues PCB Layout ONLY! works very closely with one of the world's foremost signal integrity
engineers, Robert Cutler. Robert develops CAD layout rules based on simulation results and works closely with our PCB
Designers in order to ensure that formulated design guidelines are properly implemented and that performance vs.
routeability tradeoffs can be made in real time with minimal schedule impact.
As part of his work, Robert was instrumental in the development of the CompactPCI specification that was accepted by
the PICMG as of 12/1/95. A unique termination scheme was developed that effectively damps the bus without adversely
impacting bus speed. GigE, KR, PCIeG2, XAUI, and serial channels up to 12+Gbps are among the technologies that he is
simulating and helping to implement in telecom and networking systems. This work involves modeling passive channels in
the frequency domain using various board substrates (FR406, Nelco 4000-13/13SI, Megtron 6, etc.) and connector systems
to help tradeoff performance vs. cost for the specific design. 3D modeling of via and launch structures is performed
using Ansoft HFSS, a 3D field solver. Robert’s work includes simulating DDR2 & DDR3 interfaces using both modules and
stand alone SDRAM chips.
Robert has been consulting in the field of interconnection technology since 1984 and his experience includes electrical
design, packaging, and production. The primary focus of his work is simulation and analysis of high-speed interconnect
at both the board and backplane level. Robert holds a B.S. in Electrical Engineering from Carnegie-Mellon University.
Published articles include:
Reducing Development Time in High Performance Computing Systems for the High Performance Computing Symposium in
1995.
Simulating Hot Swap in CompactPCI in January 1999 issue of Computer Design.
Reducing Chassis System Costs Without Sacrificing Performance and Bandwidth in the October 2003 EE Times Net Seminar
series.
A partial list of signal integrity analysis clients includes:
- Alcatel-Lucent
- Amphenol
- Boeing
- Ciena
- Cisco
- Ericsson
- Extreme Networks
- General Dynamics
- IBM
- Intel
- LSI Logic
- McAfee
- Motorola
- Nokia
- Nortel
- PICMG
- Qualcomm
- Raytheon
- Spirent
- Sun Microsystems
- Tellabs
- VITA
- Vitesse
| Signal Integrity Analysis & Modeling Services |